A high speed 8b “Naffziger” adder making use of Ling’s equations has been designed and simulated in a 1.5u process with two layers of metal.  The 8b adder is comprised of 606 transistors and occupies 1122x840μm or .944mm²  A simulated 8b add yields a result in <5ns or about 10FO4 delays.  The fall time is <2ns.  The maximum clocking frequency is 150Mhz.  At the time of writing, the device suffers from charge sharing and voltage level problems.